myCACTI: A NEW CACHE DESIGN TOOL FOR PIPE- LINED NANOMETER CACHES

As transistors continue to scale down into the nanometer regime,device leakage currents are becoming the dominant cause of powerdissipation in nanometer caches, making it essential to model theseleakage effects properly. Moreover, typical microprocessor cachesare pipelined to keep up with the speed of the processor, and theeffects of pipelining overhead need to be properly accounted for.In this paper, we present a detailed study of pipelined nanometercaches with detailed energy/power dissipation breakdowns showingwhere and how the power is dissipated within a nanometer cache. Weexplore a three-dimensional pipelined cache design space thatincludes cache size (16kB to 512kB), cache associativity (direct-mapped to 16-way) and process technology (90nm, 65nm, 45nm and32nm).Among our findings, we show that cache bitline leakage is increas-ingly becoming the dominant cause of power dissipation in nanome-ter technology nodes. We show that subthreshold leakage is the maincause of static power dissipation, and that gate leakage is, surpris-ingly, not a significant contributor to total cache power, even for32nm caches. We also show that accounting for cache pipeliningoverhead is necessary, as power dissipated by the pipeline elements isa significant part of cache power.